Low - Power Split - Radix Fft Processors

To design a split radix fast Fourier transform is an ideal person for the implementing of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processor, an efficient addressing scheme for FFT data as well as twiddle factors is required. The signal flow of SRFFT is the same as a redix-2 FF, and conventional address generation scheme of FFT data could also be applied to SRFFT however, SRFFT has irregular locations of twiddle factor and forbids the application of redix-2 address generation methods. This brief presents shared-memory low-power SRFFT processor architecture. We show that SRFFT can be computed by using a modified radix-2 butterfly unit. The butterfly unit exploits the multiplier-gating technique to save dynamic power at the expense of using more hardware resources. In addition, two novel address generation algorithms for both the trivial and nontrivial twiddle factors are developed. Simulation results show that compared with the conventional radix-2 sharedmemory implementations, the proposed design achieves over 15% lower power consumption when computing a 768-point complex-valued transform.